搜索资源列表
ARM-Verilog-HDL-IP-CORE
- ARM Verilog HDL IP CORE， ARM IP核，采用verilog编写-ARM Verilog HDL IP CORE, ARM IP core, using verilog write
sdr-sdram-verilog
- SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA
fpga-jpeg-Verilog
- jpeg ip核解码器，可以用来解码jpeg，verilog源代码-jpeg ip core for verilog HDL
8051core-Verilog
- 基于Verilog的 8051 IP核 内含 Testbench-The 8051 IP core based on Verilog
color-correction-using-verilog
- FPGA Implementation of Color Correction Core using Verilog
FPGA IP cores
- FPGA IP cores on verilog for USB CY7C68013, VGA, Ethernet DM9000A, Sound WM8731.
aes-core-include-testbentch
- aes core的verilog代码，包含测试代码和波形文件-aes core verilog code including testbentch
FPGA-Prototyping-By-Verilog-Examples
- HDL (hardware descr iption language) and FPGA (field-programmable gate array) devices allow designers to quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify operation of the physical impl
USB-IPcore-Verilog
- USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
jesd204
- xilinx平台 jesd204核例化使用示例(Xilinx platform jesd204 core example of the use demo)
tdc-core-master
- TDC的HDL实现代码，在SPARTAN6平台上验证过。(The HDL implementation of TDC function, verified in spartan 6 platform.)
ddr3_rw_ctrl
- verilog基于DDR3 xilinx IP核 的DDR3的读写控制，方便学习(it is based on DDR3 IP core of xilinx)
hdl-2014_r2.tar
- AD9361 IP 核，Linux版本，Vivado2014.2(AD9361 IP core, used on Linux, Vivado2014.2.)
hdl-2014_r2
- AD9361 IP核，Windows版本，Vivado2014.2(AD9361 IP core, used on Windows, Vivado2014.2)
hdl-2015_r2.tar
- AD9361 IP核，Linux版本，Vivado2015.2(AD9361 IP core, used on Linux, Vivado2015.2)
hdl-2015_r2
- AD9361 IP核，Windows版本，Vivado2015.2(AD9361 IP core, used on Windows, Vivado2015.2)
hdl-2016_r2.tar
- AD9361 IP核，Linux版本，Vivado2016.2(AD9361 IP core, used on Linux, Vivado2015.2)
hdl-2016_r2
- AD9361 IP核，Windows版本，Vivado2016.2(AD9361 IP core, used on Windows, Vivado2016.2)
8051-master
- 设计兼容51的指令集的处理器架构 编写兼容51处理器的Verilog代码 仿真 验证测试处理器的功能和性能(The design includes a processor whose instruction set is compatible to the industrial standard 8051 and its FPGA implementation. Through the analysis of instructions, I determine the CPU inte
Beautiful Restful API in ASP.Net Core
- restfull api for the team to beryfy what is the p[robme